Apple II Computer Info
switching. Decoding the slot ROM (Cnxx) could force a certain bank (such as
bank zero which would presumably always be there). The PLD could also
convert the R/W line to /OE and /WE lines for memory.
You don't need to use all this space, but at least make it available...
Lets see...
To make all of this happen, you need /IOSEL, /IOSTRB & /DEVSEL for the 3
memory spaces
you need the 8 data bus lines to latch a bank number
(if you wanna make it simple make this read only)
A7:0 can go straight through to the memory chips...
A10:8 need to be latched (and driven) if you want to
force Cnxx accesses to a certain bank
you need to produce the high 8 address lines
(latched from the data bus/forced by /IOSEL)
you need to produce at least one /CS line
you need to convert R/W into /OE and /WE
adding that up you get 3 + 8 + 0 + (3 + 3) + 8 + 1 + (1 + 2) = 29 available
I/Os
This will fit comfortably in a 44-pin PLCC (socketable) package for under
$10 and will address all locations ('cept for the 256 CFFF locations (one in
each bank)) of a 512Kx8 FLASH (non-volatile memory) or SRAM. Smaller parts
will just 'wrap around in the available banks.
There are still outputs available in the same package for decoding other
locations in the C0[n+8]x range for other devices or purposes.
If you want to get fancy you could use the 7M clock to generate /CAS and
/RAS signals for DRAMs but this would require a larger package.
Going to a 68-pin PLCC package (or 84-pin PLCC) would give you enough I/Os
to decode almost anything.
If you were to produce some generic 'application-specific' logic parts you
might as well do it properly...
cheers
ntt@dove
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Newsgroups: comp.sys.apple2
Subject: Re: Hardware Project
Date: 16 Nov 98 22:03:27 GMT
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Apple II Computer Technical Information : Apple II Family Hardware Info
ftp://ground.ecn.uiowa.edu/2/apple2/miscinfo/hardware : May 2001 : 175 of 572
(22 pages)
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